This invention relates to a processor array comprising a plurality of processors. The processor array is for use in carrying out real-time digital processing of an array input signal which is typically a digital video signal. The real-time digital processing is, for example, spatial or temporal filtering of the digital video signal, interframe coding, or intraframe coding. The filtering and the interframe and the intraframe coding are known in the art.
A processor array is disclosed in a prior patent application which was filed June 9, 1987, by Hidenobu Harasaki, Ichiro Tamitani, and Yukio Endo for assignment to the present assignee. The above-named Ichiro Tamitani is the instant applicant. In the prior patent application, the processor array is called a real-time video signal processing device and comprises one or two processors, each processor comprising a plurality of processor modules. The processor and the processor module are named a video signal processor and a signal processing module, respectively, in the prior patent application.
Various conventional processor arrays are described in the prior patent application. In any one of the conventional processor arrays and of the processor array of the prior patent application, each processor is for processing an input digital video signal having a frame period into an output digital video signal with the input digital video signal divided into a succession of principal blocks.
Each principal block may be in a form of one picture of the input digital video signal and has therefore a picture period which is equal to the frame period. That is, the input digital signal is in the form of a succession of the principal blocks. Each principal block is divided into a predetermined number m of partial blocks so that the partial blocks overlap one on another at their peripheral parts, where m represents a predetermined integer which is greater than one.
Alternatively, each principal block may be in another form of a preselected number n of scanning lines of the input digital video signal, where n represents a positive integer. In this case, each principal block has a time duration which is shorter than the frame period. In this case, division of each principal block is similar to that of the above-mentioned case except that each principal block is divided into the predetermined number m of partial blocks with each scanning line divided into the respective partial blocks.
A plurality of processor modules of each processor are for processing the respective partial blocks of each principal block into processed signals during the picture period, respectively, when each principal block is composed of one picture. When each principal block is composed the preselected number n of scanning lines, the processor modules of each processor process the respective partial blocks of each principal block during the time duration, respectively.
In either processor array, it is possible to easily carry out real-time processing by increasing the number of the processor modules of the processor array.
Any one of the conventional processor arrays and of the processor array of the prior patent application is, however, defective in that it is impossible to change the number of the processor modules of the processor array without modification of the architecture of the processor array. From this viewpoint, it is desirable to easily connect a plurality of the processors in parallel.
It is also desirable to easily connect a plurality of the processors in series, that is in a pipeline fashion. More specifically, in motion-compensated interframe coding, it is general that noise reduction process, such as spatial and/or temporal filtering of the input digital video signal, is carried out as a preceding process before the input digital video signal is subjected to interframe coding used as a succeeding process. The filtering is carried out to elevate correlation between pictures. In such a case, successive processing of the filtering and the interframe coding must be carried out by two processors connected in series or in cascade. This is because the interframe coding should be carried out so that the partial blocks overlap one on another at their peripheral parts, although it is preferable for the partial blocks to fail to overlap one on another in the filtering so as to save superfluous calculation. This problem on the overlap is known in the art.
Moreover, without modification of the processor array, either processor array can not be operable in a case where the preceding and the succeeding processes are different in complexity of processing.